1. Field of Invention
The present invention relates to a bumpless chip package. More particularly, the present invention relates to a bumpless chip package having a conductive channel to shorten the transmission path between the chip and the panel-shaped component and to prevent the edge of the chip from cracking due to high operational temperature.
2. Description of Related Art
With rapid advancement of electronic technology, the chip package technology is developing towards miniature size and high density to meet various requirements such as high processing speed, multifunction, high integration, light weight, and low cost in the electronic devices. Generally, in the conventional ball grid array (BGA) package technology, the package substrate is applied as the carrier of IC chips, and electrical connection technology such as flip chip bonding or wire bonding technology is applied to electrically connect the chip to the top surface of the package substrate, and a plurality of solder balls are disposed on the bottom surface of the package substrate in area array. Accordingly, the chip may be electrically connected to the electronic apparatus in the next level, e.g. printed circuit board etc, through the inner circuit of the package substrate and the solder balls at the bottom of the package substrate.
However, in the conventional BGA package technology, the package substrate of high layout density combined with electrical connection technology such as flip chip bonding or wire bonding results in a long signal transmission path. Thus, a bumpless build-up layer (BBUL) chip package technology has been developed, wherein the process of flip chip bonding or wire bonding for connecting the chip to the package substrate is skipped, but a multi-layered interconnection structure is fabricated on the chip, and electrical contacts such as solder balls or pins are fabricated on the multi-layered interconnection structure in area array to electrically connect to the electronic apparatus of the next level.
Referring to FIG. 1, a cross-sectional view of a conventional bumpless chip package is shown. The conventional bumpless chip package 100 includes a chip 110, an interconnection structure 120, a panel-shaped component 130, and a plurality of solder balls 140. The chip 110 is disposed on the panel-shaped component 130, and the panel-shaped component 130 is used as a base plate or a support layer. The chip 110 has a plurality of point-shape pads 112 arranged in area array and disposed on an active surface 114 of the chip 110. In addition, the point-shape pads 112 include signal pads, ground pads, and power pads, etc.
Moreover, the interconnection structure 120 is also disposed on the panel-shaped component 130, wherein the interconnection structure 120 is formed on the panel-shaped component 130 in a build-up process. The interconnection structure 120 has an inner circuit 122 and a plurality of contact pads 124 disposed on a contact surface 126 of the interconnection structure 120. Note that the point-shape pads 112 and the contact pads 124 are electrically connected through the inner circuit 122.
In addition, the interconnection structure 120 includes a plurality of dielectric layers 128, a plurality of conductive vias 122a, and a plurality of circuit layers 122b. The conductive vias 122a and the circuit layers 122b form the aforementioned inner circuit 122. The dielectric layers 128 and the circuit layers 122b are staggered, and the conductive vias 122a pass through the dielectric layers 128 respectively. Two circuit layers 122b are electrically connected to each other through at least a conductive via 122a. In addition, the solder balls 140 are disposed on the contact pads 124 to electrically connect to the electronic apparatus of the next level (not shown).
However, the edge of the chip will easily crack due to the high temperature produced during operation and the difference of coefficient of thermal expansion (CTE) between the chip and the panel-shaped component, thus causing damage to the integrated circuit on the active surface of the chip, and the proper operation of the chip will be adversely affected.